Tetron Qubit (Topological Superconductor)

The tetron is a topological qubit design encoding quantum information in the joint fermion parity of four Majorana zero modes (MZMs) arranged in an H-shaped semiconductor-superconductor heterostructure. The qubit states $|0⟩$ and $|1⟩$ correspond to even and odd total parity of MZM pairs, and are topologically protected against local perturbations. The tetron is the architecture behind Microsoft’s Majorana 1 processor (2025).

Figure

Description

Architecture

Four MZMs are hosted at the endpoints of two parallel topological superconductor segments connected by a trivial superconducting bridge (forming an “H” shape). The logical qubit is encoded in the parity degree of freedom:

$|0_L⟩=|p_{12}=+1,p_{34}=+1⟩,|1_L⟩=|p_{12}=-1,p_{34}=-1⟩$

where $p_{ij}$ is the fermion parity of MZM pair $(i,j)$.

Gate operations

• Measurement-based braiding: Joint parity measurements of MZM pairs implement effective braiding without physically moving quasiparticles
• Parity readout: Quantum dot sensors coupled to MZM pairs measure parity via charge sensing
• Clifford gates: Complete Clifford group from single-qubit parity measurements + two-qubit joint measurements

Microsoft Majorana 1

Microsoft’s 2025 Majorana 1 processor implements 8 tetron qubits using InAs/Al heterostructures (“topoconductors”). Key claims: topological gap protocol passed, controlled MZM parity, and path toward 4×2 arrays with entanglement. The approach targets ~10× reduction in QEC overhead compared to conventional superconducting qubits.

Hamiltonian

Low-energy effective Hamiltonian for four MZMs:

$H_{\text{eff}}=i{ϵ}_{12}{\gamma }_1{\gamma }_2+i{ϵ}_{34}{\gamma }_3{\gamma }_4$

where ${\gamma }_i$ are Majorana operators (${\gamma }_i^{†}={\gamma }_i$, $\{{\gamma }_i,{\gamma }_j\}=2{\delta }_{ij}$) and ${ϵ}_{ij}$ are exponentially suppressed overlap energies. Topological protection: ${ϵ}_{ij}\propto e^{-L/\xi }$ where $L$ is the separation and $\xi$ the coherence length.

Performance Metrics

Metric	Value	Notes	Fidelity reference
Topological gap	~20–40 μeV	InAs/Al topoconductor	aghaee-2025-majorana-1
MZM count	4 per tetron	H-shaped device	karzig-2017-tetron
Parity lifetime	Not yet reported	Key open metric	—
QEC overhead reduction	~10× claimed	vs. transmon surface code	aghaee-2025-majorana-1

Scaling Considerations

• Measurement-only topological QC: No physical braiding needed — simplifies device layout
• Modular arrays: 4×2 tetron arrays planned as building blocks for larger processors
• QEC synergy: Topological protection at physical level reduces logical overhead
• Materials challenge: Requires pristine semiconductor-superconductor interfaces with hard induced gap

Linked Papers

• karzig-2017-tetron
• aghaee-2025-majorana-1

Related Entries

• majorana-topological-qubit
• planar-josephson-junction-qubit
• surface-code-logical-qubit