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Interferometric Single-Shot Parity Measurement in an InAs-Al Hybrid Device

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Microsoft’s demonstration of the Majorana 1 processor: an 8-qubit topological processor using InAs/Al heterostructures (topoconductors) in the tetron geometry. Reports interferometric single-shot parity measurement of Majorana zero modes, passing the topological gap protocol. Represents the first hardware implementation of the Karzig et al. (2017) tetron architecture.

Key Results

  • 8 tetron qubits on InAs/Al topoconductor platform
  • Interferometric single-shot parity readout
  • Topological gap protocol passed
  • H-shaped device geometry with 4 MZMs per qubit
  • Path toward 4×2 arrays with inter-qubit entanglement

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